There are several sources of error that contribute to non-ideal performance of circuits, such as bias circuits, and many of these sources of error cannot be removed by the designer of such a circuit. Such sources of error include errors such as, but not limited to: mechanical stress during the manufacturing of the die; mechanical stress during packaging; and imperfections during manufacturing of the die resulting in variant electrical parameters. Such sources of error affect the circuit in the form of process variation and mismatch.
Process variation is well known in the art, and is essentially variation of the electrical parameters of a class of devices from part to part. Mismatch error is also well known in the art, and is essentially electrical parameter variation from an average value in devices that are expected to have matching values. Mismatch error only has meaning among devices in a single part. For this reason, it is also known as intra-die electrical parameter variation.
In a typical bias circuit, such as a scalable bandgap voltage generator, a bias voltage is generated using three types of devices in the signal path: metal oxide semiconductor field effect transistors (MOSFETs), bipolar junction transistors (BJTs), and resistors. During the manufacture of a circuit, the effect of mismatch and process variation on all three of these device types (MOSFETs, BJTs, and resistors) are present and should be considered. Some of these error sources can be removed by design and some can not. In bias circuits for example, BJT process spread cannot be removed by design and is the traditional error source requiring trim. This is because the complementary to absolute temperature component of the bias circuit is typically generated by a single BJT device. As such, the VBE output (the CTAT component) of the BJT device has a gain (slope) variation from the ideal gain across a given temperature range. However, it is commonly known that the gain can be adjusted toward the ideal slope by trimming, for example, the current proportional to absolute temperature (IPTAT) that biases the CTAT BJT device. Other techniques for performing trimming to adjust the gain of the BJT toward ideal are also well known in the art. All of these techniques take advantage of the fact that the BJT process spread on the VBE generating device produces a pure gain error. A pure gain error results in the y-intercept of the signal versus temperature line remaining stable while the slope varies. Thus, when the BJT process error is the only error in a circuit, it can be removed by gain trimming while the circuit remains at a single temperature.
Likewise, the effect of manufacturing induced mismatch is often a critical source of error with respect to MOSFETs and resistors. MOSFET mismatch in particular, is a large source of error in circuits, such as scalable bandgap circuits, which perform extensive mirroring using MOS devices. With respect to MOS devices, mismatch on amplifier inputs and current mirrors alters the y-intercept of an expected voltage with respect to temperature, but leaves the slope relatively unchanged. In other words, mismatch error in MOS devices causes a pure offset error/absolute value error. For example, in a bandgap generator, MOSFET mismatch can cause an error on the bandgap voltage that is effectively a consistent value (such as 10 millivolts too high or 20 millivolts too low) across a given temperature range. When MOSFET error is known or is the only error present, well known trimming techniques can remove MOSFET mismatch error through trimming while the circuit remains at a single temperature.
A problem arises however, when both gain error and offset error exist simultaneously in a circuit. With multiple simultaneous sources of error, some of which result in a gain error and some of which result in an offset error, present manufacturing techniques are unable to sort these errors apart from one another while the circuit remains at a single temperature. Two techniques have been widely used to deal with such a problem, but each has drawbacks.
In the first technique, measurements of circuit operating parameters are made at two separate temperatures. This allows the gain component of the error to be observed, and thus separated from the offset component. This technique however adds time, expense, and complexity to a manufacturing process. Time is added because, testing and trimming on a particular component takes longer due to waiting for a component to stabilize at a second temperature so a second set of measurements can be made. Expense and complexity are added by creating a manufacturing line which must operate at two separate temperatures instead of one constant temperature. Expense and complexity are also added by handling a circuit twice and performing extra measurements on a circuit under test and calibration.
In the second technique, during manufacturing, a process variation induced gain error is calibrated by direct measurement or else is roughly trimmed while offset error is ignored. When the circuit is later in operation, such as by a customer, dynamic element matching techniques (otherwise known as chopping), are used to actively average out mismatch induced offset errors. This second technique is fairly effective, but has several drawbacks. One drawback is that trimming the process error of the BJT individually requires very precise temperature control of the manufacturing environment, often in excess of capability. Ignoring other errors all together and trimming the BJT process variation by monitoring the bandgap voltage is also problematic because other error types may be exacerbated by the trim. Another drawback is that dynamic element matching is a power hungry error reduction technique that causes the circuit to consume additional power. Increased power consumption becomes even more apparent, when the output of a circuit needs to be sampled at a high frequency. In such a case, the dynamic element matching techniques involved are also typically performed at a high frequency, which causes the circuit to consume even more power. Yet another drawback is that such dynamic element matching techniques are often more complex to implement and manage compared to continuous DC signals.
As can be seen, current manufacturing methods and processes provide for some solutions to deal with situations where the previously described process variation induced gain errors and mismatch induced offset errors are simultaneously present in a circuit. However, these current methods often inadequately address the errors or else are costly, complex, and/or time consuming to implement.